The present invention relates to an input buffer for a semiconductor memory device. More particularly, the present invention relates to a write signal input buffer receiving an externally supplied write enable signal, and providing a write drive signal as an internal control signal within the memory device.
Conventional semiconductor memory devices typically include various input buffers receiving externally generated address signals, data signals, and control signals. Each buffer acts as an input stage to circuits within the memory device, receiving the external signals, converting the external signals into compatible internal signals, and providing the internal signals to respective circuits within the memory device. Of particular relevance, conventional memory devices include a write enable signal input buffer (hereinafter referred to as "write signal input buffer") which receives a write enable control signal, and provides a corresponding master clock control signal which drives, or enables, respective circuits within the memory device. The write enable signal is typically supplied from a system or CPU external to the memory device. The master clock signal timing, and thus the entire "enablement" sequence of the respective circuits within the memory device is determined according to the timing Of the write drive signal. Examples of internal circuits efficiently enabled or driven by a master clock signal derived from a write enable signal include data transfer circuits, control circuits, data input/output circuits, etc.
Unfortunately, the actual implementation of internal memory device circuits whose operation is enabled by the write drive signal presents a very difficult problem. The problem arises in that the respective circuits must be designed such that they are synchronous in operation with the timing waveform of the write drive signal. In other words, the externally supplied write drive signal defines the enablement window during which the internal circuits within the memory device are operated.
As is well known, signals such as the write drive signal supplied from the overall system controller or CPU have very short enabling intervals. Accordingly, internal signals provided by input buffers, responsive to signals such as the write drive signal, are enabled during a correspondingly brief interval. Controlling the operation of internal circuits in accordance with the write drive signal during this extremely short interval is rarely possible in a highly integrated, semiconductor memory device. This is true because of the very tight timing margins required for data transfer within the memory device, and because of the risk of falsing, i.e., the erroneous transition of data in response to a spuriously generated signal.
To solve such problems, a method of lengthening the "enabling" interval of a write drive signal has been proposed, wherein a latch circuit is added to the input buffer described above. As shown in FIG. 1, regardless of the actual enabling interval of an externally generated write enable signal WE, the latch circuit may "hold" the signal for a predetermined period of time.
Referring to FIG. 1, the write enable signal WE is externally supplied to WE(not) terminal 2. Assuming that WE is enabling when "high" or "1", the voltage apparent at node 14 rises to V.sub.cc when WE is applied. In response to the positive voltage at node 14, the output at NOR gate 16 becomes "low" or "0." Coincident with the application of WE, if a column enable signal .phi.C is applied in "high" a state as a clocking input, the output at NOR gate 20 becomes "high." This result is output as write drive signal .phi.WR.
The output of NOR gate 20, .phi.WR, is feedback to NOR gate 16 via line 24. Thus, .phi.WR remains "low" beyond the duration of the externally supplied write enable signal WE, and .phi.WR is "latched" by the inclusion of line 24 within the conventional input buffer. The foregoing feedback/latching scheme addresses, at least in part, the problem of designing internal circuits within the memory device controlled, or enabled by the write drive signal .phi.WR by providing a write drive signal .phi.WR having a longer enabling interval.
The operation of the conventional input buffer, shown for example in FIG. 1, and the resulting write drive signal .phi.WR are further illustrated in steps e1 through e5 in the operational timing diagram shown in FIG. 2. As shown in e5 of FIG. 2, the write drive signal .phi.WR follows the voltage at node 14 and goes "high" in accordance with the column enable signal .phi.C and write enable signal WE.
Despite the improved performance over the conventional input buffer not having a feedback/latching path, the write signal input buffer shown in FIGS. 1 and 2 has at least one serious problem. Typical semiconductor memory devices include a data output buffer and a data output driver (not shown) which form an output stage supplying data outside the memory device during read operations. As is well known, the foregoing output stage operates synchronously with a column address strobe signal CAS(not) as shown in steps e1, e6, e7, and e8 of FIG. 2. When the data output driver is turned on, large ground noise is induced by the switching operation of transistors constituting the data output driver. The presence of the ground noise causes the gate-to-source voltage V.sub.GS of transistor 6 in FIG. 1 to fall below the switching threshold regardless of the presence of the write enable signal WE. As a result, the voltage at node 8 rises above the 1/2V.sub.cc, and node 14 becomes "high" as indicated by the dotted line in step e9 of FIG. 2. The "high"-state of node 14 causes the write drive signal .phi.WR to go "high" as shown in step e10 of FIG. 2. Accordingly, the write drive signal .phi.WR "falses" as a result of the ground noise generated by operation of the data output driver. The false .phi.WR output falls outside the timing sequence of the externally provided write enable signal WE. "As a result, read/write operation of the memory device is incorrectly performed. That is, during false operation of .phi.WR, even if the write enable signal WE is correctly supplied, node 14 in FIG. 1 is "blocked" by ground noise such that a write operation cannot be performed during the proper "write" interval.
The write signal input buffer described above with respect to FIGS. 1 and 2 is similar to the write signal input buffer found, for example, in the 1M DRAM product TC51100 or TC51101 manufactured by Toshiba Co. In particular, the Toshiba devices include the feedback/latch circuit defined by line 24 in FIG. 1.